Various types of active microelectronic components operate best in an open area cavity. Such active components include Surface Acoustic Wave (SAW) devices and Microelectromechanical Systems (MEMS) devices. These devices are very sensitive to moisture and particulates, which can cause device failure, alter performance, and decrease reliability. The traditional method of protecting these devices has been to encase the device in a ceramic package, a metal lid, or through wafer-to-wafer bonding that creates a hermetic cavity necessary for proper long-term performance. This approach is successful in protecting the device, but results in an increase in die area significantly above and beyond the active area footprint. In addition, ceramic packages are expensive and constitute a significant portion of the total cost of the entire packaged device. Furthermore, placing these devices within a ceramic package requires wafers to be shipped to a second facility for further processing before they are able to be finally tested and integrated, thereby greatly increasing the required manufacturing time. Many of these components play a significant role in circuits, which are primarily implemented in semiconductor modules.
In an effort to reduce fabrication cost, complexity, and cycle time, as well as the overall footprint of the microelectronic module, efforts have been made to create integrated hermetic cavities for active components at the wafer level. This would eliminate the need for the cost and time associated with the ceramic packaging process and would keep all of the operations in die processing from bare substrate to final testing at a single facility. In many instances, creation of the integrated hermetic cavity requires significant variations from the fabrication process used to form microelectronic devices without hermetic cavities. These variations add cost, complexity, and time to the fabrication process of the microelectronic device. One such proposal is provided in U.S. Pat. No. 6,877,209 to Miller, wherein a polysilicon material is used as a sacrificial layer, which is removed using Xenon Difluoride (XeF2) to form a cavity. However, equipment that works with Xenon Difluoride is not commonly found in microelectronic fabrication facilities. As such, the use of Xenon Difluoride has proven to be costly and injects inefficiency into the fabrication process. In addition, polysilicon films are typically deposited by the use of Chemical Vapor Deposition equipment or by sputtering. These techniques have the disadvantage of requiring high temperatures or long deposition times, both of which are detrimental when applied to SAW filters or MEMS devices. The thickness uniformity of the resulting films is also historically poor with this type of equipment. Finally, the polysilicon films tend to be conformal to the underlying topography. Therefore, when polysilicon is used as a sacrificial layer, the underside of any subsequent films used as a cap layer will not be planar, leading to variations in the height of the cavity and potential issues for yield or reliability failures of finished die.
An issue with integrated cavities is that the cavities are prone to collapse due to high pressures associated with the fabrication process. An extra thick cap layer over the cavity is employed by Miller to increase structural integrity. However, providing a cap layer sufficiently thick to survive the fabrication process results in excessively long deposition times and an unduly thick package. As any film that is deposited must subsequently be etched through in order to provide access to bondpads and the associated circuitry of the device, unduly thick films will necessitate unduly long etch times, further increasing the length of the process. Additionally, the thickness and thickness variability of the films can cause issues with flip-chip processing, as mold compound that is injected inbetween adjacent flip-chip bumps or posts may not flow uniformly and repeatably, and the thickness of the dielectric might undesirably require that flip-chip bump and post height to be increased.
As such, there is a need for a cost efficient process to create a microelectronic device having an integrated, hermetic cavity to enclose active devices at the wafer level.